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We are seeking highly-motivated individuals with 5+ years of direct digital ASIC design experience. HDL knowledge and Synopsys design compiler experience is required. Verilog experience preferred. Computer architecture and/or networking knowledge is strongly desired and analog and mixed signal experience is a plus. A BS in EE or CS is required. Strong computer skills in a UNIX environment are required. Proficiency with C, Perl or Matlab are also highly desirable. Broadband, modem hardware/software or wireless experience is a plus.
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