64 State Viterbi Encoder/Decoder Core
 

Summary            

The 64 state Viterbi Encoder/Decoder is intended to be used in applications as an integrated replacement for the Qualcomm Q1900 64 State Viterbi/Trellis decoder and is provided as synthesizable Verilog HDL.  Full documentation, test benches, and Synopsys development scripts are provided.  The design has been optimized for power/space minimization.  Design customizations can be performed by the customer or by Alantro Communications to suit the customer application.  Since our decoder core HDL is computer generated, we can quickly optimize the design further to allow higher data rates or even more compact implementations.

Selectable Puncturing Rates: 1/3, 1/2, 2/3, 3/4, 7/8, or fully programmable using external puncturing logic.

Automatic Phase Synchronization:

BER monitoring using both correction count and path metric accumulator growth.

Operates using either 4-bit soft decision or 1-bit hard decision input.

Fully synchronous design.

Available as synthesizable Verilog-HDL source.

Includes test-vector files, as well as Verilog test benches.

Includes Synopsys synthesis scripts.

Intended replacement for Qualcomm Q1900 Viterbi/Trellis Decoder.

Customization available per request.

Viterbi Mode complies with INTELSAT IESS-308 and INTELSAT IESS-309.

Standard design requires approximately 26,000 gates in addition to 16k bits of single port RAM (with 96 symbol trace-back depth).

Requires 5 clocks per input symbol. (Other versions available upon request.)

Variable trace-back depth, either hard coded or programmable.

160 symbol delay at 96 symbol trace-back depth.