HDSL-2 FEC Decoder / Encoder Core

Summary           

The HDSL-2 FEC provides encoder and decoder functionality for the emerging HDSL-2 standard.  The encoder provides a byte interface and 2's-compliment PAM symbol output. Optional multi-rate modes are also supported, which allow a reach / rate optimization.  The decoder provides a 512 state Viterbi core, data formatting, and channel quality monitoring circuitry.

The decoder receives 2's-compliment symbol values from the demodulator and provides error corrected byte values on its output.  It contains the Thomlinson decoder, Viterbi decoder, and optional Multi-rate support circuitry.

The encoder provides the BCC encoding, as well as the circuitry for optional Multi-rate support.

The design is provided in synthesizable Verilog HDL.  The design is fully synchronous and requires a clock which is 144X the incoming symbol rate (approx. 100MHz).  The HDL is compatible with full scan testing.  Included with the design are extensive test benches, vectors, Synopsys synthesis scripts, Makefiles, and extensive documentation.

Compliant with emerging HDSL-2 standard.

Channel condition monitoring logic.

Synthesizable Verilog HDL.

Trace-back depth programmable from 4 to 64 symbols.

Optional Multi-rate support.

BER performance: 10e-7 at 22.5dB SNR.

Extensive Matlab models of decoder for system simulation.

Complete Verilog test benches, test vectors, and documentation.

Synopsys synthesis scripts.

Approximately 30k gates and 72k bits of single-port RAM.

Low latency of 68 symbols (at trace-back depth = 64).

Immediate availability.