ITU-T J.83-B / MCNS 64/256 QAM FEC Core

Summary            

The FEC core is intended for use in digital cable demodulator systems, as well as for applications such as MCNS Compliant Cable Modems and Digital Broadcast Television.  The FEC accepts 2's-compliment format data with 4 "soft" decision data bits for I and Q.  The output of the FEC is an error corrected data stream, MPEG optional.  Status and control signals are also available.

Automatic phase synchronization and monitoring.

Integrated 16 state Viterbi decoder.

Standards Compliance: MCNS DOCSIS, ITU-T J.83-B, IEEE 802.14.

Integrated 3-error correcting Reed-Solomon decoder.

Includes MPEG bit stream synchronization circuit.

BER monitoring, using path metric accumulator growth or Reed-Solomon statistics.

Supports all Interleaving modes, using either an internal or external RAM, or both.

Fully synchronous design.

Available as synthesizable Verilog-HDL source.

Includes test-vector files, as well as Verilog test benches.

Includes Matlab models for system integration and simulation.

Includes Synopsys synthesis scripts.

Customization available per request.

Proprietary FEC algorithms give highest possible performance.

Performance:

256 QAM 10 -8 BER @ 27.3 dB SNR  64 QAM 10 -8 BER @ 21.2 dB SNR

    

Requires 8 clocks per input symbol (approx 50MHz).

FEC area requirements: approx 95k gates with 10k bits of single port RAM.

RAM requirements for de-interleaver range from 448 x 7 bits up to 64k x 7 bits, depending upon which modes are supported.