The Reed-Solomon error correction core is used in DVB, HDTV, Satellite, and RF applications. It can be used either in concatenated systems in conjunction with a Viterbi Decoder, or as an independent FEC in applications where it is necessary to correct bit errors in blocks of received data. Various configurations of the decoder can be quickly generated by our RS generator program. As standard configurations, we offer GF 256 decoders, which allow configurable primitive polynomial, either error decoding or erasure decoding, with block sizes up to 256 bytes with T=8,10, or 16. It is provided as synthesizable Verilog HDL. Full documentation, test benches and Synopsys development scripts are provided. Design customizations can be performed by the customer or by Alantro Communications to suit the customer application. Since our decoder core HDL is computer generated, we can quickly optimize the design for custom applications.
- Block sizes up to 256 bytes.
- Either erasure or correction mode.
- R up to 32, thus either detecting up to 32 byte errors or correction of up to 16 bytes.
- Fully synchronous design.
- Available as synthesizable Verilog-HDL source.
- Includes test-vector files, Verilog test benches.
- Includes Synopsys synthesis scripts.
- Customization available per request.
Alantro Communications, Inc.